Field of the Invention:
The present invention relates to methods and apparatus for packaging single and multiple semiconductor dice to provide an array-type pinout. In particular, the present invention relates to methods and apparatus for packaging semiconductor dice in the form of chip scale, ball grid array packages.
State of the Art:
Semiconductor dice are conventionally packaged individually in plastic or, less commonly, ceramic packages. Packaging supports, protects, and dissipates heat from the semiconductor die and provides a lead system for power and signal distribution to and from the semiconductor die. The die package also facilitates bum-in and other testing of each semiconductor die prior to and after its assembly with higher level packaging.
One type of integrated circuit (IC) or semiconductor die package is referred to as a “chip scale package,” “chip size package,” or merely “CSP.” These designations arise largely from the physical dimensions of the package, which are only nominally larger than the actual dimensions (length, width and height) of the unpackaged semiconductor die. Chip scale packages may be fabricated in “uncased” or “cased” configurations. Uncased chip scale packages do not include an encapsulation or other covering of the sides of the semiconductor die extending between the active surface and back side thereof and, thus, exhibit a “footprint” (peripheral outline) that is substantially the same as that of an unpackaged semiconductor die. Cased chip scale packages have encapsulated or covered sides and thus exhibit a peripheral outline that is slightly larger than that of an unpackaged semiconductor die. For example, a surface area of a footprint for a conventional cased chip scale package may be up to about 1.2 times that of the bare semiconductor die contained within the package.
A chip scale package may typically include an interposer substrate bonded to the active surface of the semiconductor die. The interposer substrate may include traces extending to contacts for making external electrical connections to the semiconductor die of the chip scale package. The interposer substrate for a chip scale package may comprise a flexible material, such as a polymer (i.e., polyimide) tape, or a rigid material, such as silicon, ceramic, glass or FR-4 or other fiberglass laminate. The external contacts for one type of chip scale package include solder balls or other discrete conductive elements protruding from the package and arranged in an array. Such a design is termed a “ball grid array” (BGA), or a “fine ball grid array” (FBGA) for such an array having a very closely spaced, or pitched, array of discrete conductive elements. BGA and FBGA packaging provides the capability for a high number of inputs and outputs (I/Os) for a chip scale package, several hundred I/Os being easily achieved if necessary or desirable.
Integrated circuit packaging surface mount technology, such as so-called “vertical surface mount packages” or “VSMP” technology, has also provided an increase in semiconductor die density on a single carrier substrate or circuit board. This results in more compact designs and form factors and a significant increase in integrated circuit density. However, many VSMP designs are somewhat costly to implement and require fairly complex and sophisticated carrier substrates. In addition, for some applications, the relatively large distance of protrusion of the VSMPs above the carrier substrate unacceptably limits the number of carrier substrates which may be inserted transversely in adjacent slots of a higher level packaging substrate, such as a PC motherboard.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the volume and thus cost of components used in packaging tend to decrease due to advances in packaging technology, even though the functionality (memory capacity and speed, processor speed, etc.) of the packaged end products increases. For example, on the average, there is approximately a 10 percent decrease in packaging component usage for every product generation in comparison to the previous generation exhibiting equivalent functionality.
Chip scale packages are thus of current interest in modern semiconductor packaging as a method for reducing the package size and cost. Further, the industry has responded to the limited space or “real estate” available for mounting semiconductor dice on a carrier substrate by vertically stacking two or more semiconductor dice, the I/Os to the carrier substrate often being provided between the lowermost semiconductor die and carrier substrate within the footprint of the stack. Therefore, it would be advantageous to provide a method and apparatus that may further reduce chip scale package size and enhance robustness of the package while at the same time reducing fabrication cost and enhancing production flexibility in combination with providing a capability to stack two or more semiconductor dice of the same or different types to increase circuit density on a carrier substrate to which such a multi-die chip scale package is attached.